1. Field of the Invention
The present invention relates to a static-type random access memory device (hereinafter referred to as "SRAM") and, more particularly, to a test mode switching circuit for a data read-out time.
2. Description of the Related Art
One of previously known SRAMs with one bit output is shown in FIG. 4. As shown in FIG. 4, a memory cell array part 41 is divided into a plurality of memory cell blocks which are memory cell arrays 41a to 41n each being further divided into four memory sections S1 to S4. A sense amplifier 42 is provided for each of the memory sections S1 to S4, and a write buffer 43 is provided also for each of the memory sections S1 to S4.
An input circuit represented by numeral 44 includes, as shown in FIG. 6, a NOR circuit 61 and a plurality of inverter circuits (hereinafter simply referred to as "Inverters") I61 to I617.
An output circuit is represented by numeral 45. As shown in FIG. 5, the output circuit 45 includes a plurality of transfer gates TR61 to TR64, an inverter I56, and an output buffer unit BF50. The transfer gate TR61 includes an NMOS transistor (hereinafter referred to as "NMOST") Q51, a PMOS transistor (hereinafter referred to as "PMOST") Q52 and an inverter I51; the transfer gate TR62 includes an NMOST Q53, a PMOST Q54 and an inverter I52; the transfer gate TR63 includes an NMOST Q55, a PMOST Q56 and an inverter I53; and the transfer gate TR64 includes an NMOST Q57, a PMOST Q58 and an inverter I54, respectively. The transfer gates TR61 to TR64 are connected with the output buffer unit BF50 through the inverter I56. The buffer unit BF50 is composed of inverters I57 to I59, a NOR gate 51, a NAND gate 52, a PMOST Q59 and an NMOST Q510.
Referring back to FIG. 4, signal lines RB1 to RB4 are read-out data bus lines connected with outputs of the sense amplifiers 42 belonging to the corresponding memory sections S1 to S4, respectively, and also with inputs of the output circuit 45. Signal lines WB1 to WB4 and WBB1 to WBB4 are write data bus lines (output signal lines of the input circuit 44) connected with the inputs of the write buffers 43 belonging to the corresponding memory sections S1 to S4, respectively.
An explanation will be given of the actual operation of the conventional SRAM device explained above. The write operation is as follows. An external signal D.sub.IN is buffered by the input circuit 44. The input buffer 44 transfers write data to the write data bus lines WB1 to WB4 and WBB1 to WBB4. One write buffer 43 corresponding to a selected address is selected from a group of the write buffers 43. The selected write buffer 43 operates to write or store the data in a selected memory cell.
The read operation is as follows. One sense amplifier 42 corresponding to a selected memory cell is selected from a group of the sense amplifiers 42. The sense amplifier 42 thus selected amplifies the data read out from the selected memory cell. For example, if a memory cell within the memory section S1 of memory cell array 41a is selected, the data is transferred to the output circuit 45 through the read data bus line RB1. Then, among transfer gate control signals .phi.1 to .phi.4 for the output circuit 45, the control signal .phi.1 is set at "L" (low level) whereas the remaining control signals .phi.2 to .phi.4 are set at "H" (high level). Therefore, the transfer gate TR61 formed by the NMOST Q51, PMOST Q52 and the inverter I51 becomes "on", whereas the transfer gate TR62 (formed by the NMOST Q53, PMOST Q54 and the inverter I52), the transfer gate TR63 (formed by the NMOST Q55, PMOST Q56 and the inverter I53), and the transfer gate TR64 (formed by the NMOST Q57, PMOST Q58 and the inverter I54) become "off", respectively. As a result, only the data on the read data bus line RB1 is transferred to a node N51. The level at this node NS1 is first inverted by the inverter I56 and then buffered by the output buffer unit BF50, so that a read data is outputted from a signal output terminal D.sub.OUT.
The above explained conventional SRAM device has the following defect. Since the conventional SRAM device reads or writes data one bit by one bit, it takes a long test time in a memory test system and takes longer time as the memory capacity increases to such as 1 mega, 4 mega and 16 mega bits.
For example, even only for reading the memory cells of 4M bits capacity successively with a clock cycle time of 1 .mu.sec, it takes 1.times.10.sup.-6 .times.4.times.10.sup.6 (sec). In practice, since memory tests of such kinds as above and other kinds are performed many times under different conditions or parameters such as different voltages, the total test time required may reach several hundred seconds, thereby significantly increasing the cost involved for such tests. The defect in the conventional SRAM device is to be solved by the present invention.